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Merge pull request #350 from lioncash/qops

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Implement the rest of the UQ* ops.
This commit is contained in:
bunnei 2014-12-27 21:15:13 -05:00
commit 3422d81f05
4 changed files with 190 additions and 26 deletions
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105
src/core/arm/dyncom/arm_dyncom_interpreter.cpp
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@ -3249,12 +3249,44 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(blx_1_thumb)(unsigned int tinst, int index)
return inst_base;
}
ARM_INST_PTR INTERPRETER_TRANSLATE(uqadd16)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("UQADD16"); }
ARM_INST_PTR INTERPRETER_TRANSLATE(uqadd8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("UQADD8"); }
ARM_INST_PTR INTERPRETER_TRANSLATE(uqaddsubx)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("UQADDSUBX"); }
ARM_INST_PTR INTERPRETER_TRANSLATE(uqsub16)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("UQSUB16"); }
ARM_INST_PTR INTERPRETER_TRANSLATE(uqsub8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("UQSUB8"); }
ARM_INST_PTR INTERPRETER_TRANSLATE(uqsubaddx)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("UQSUBADDX"); }
ARM_INST_PTR INTERPRETER_TRANSLATE(uqadd8)(unsigned int inst, int index)
{
arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
inst_base->cond = BITS(inst, 28, 31);
inst_base->idx = index;
inst_base->br = NON_BRANCH;
inst_base->load_r15 = 0;
inst_cream->Rm = BITS(inst, 0, 3);
inst_cream->Rn = BITS(inst, 16, 19);
inst_cream->Rd = BITS(inst, 12, 15);
inst_cream->op1 = BITS(inst, 20, 21);
inst_cream->op2 = BITS(inst, 5, 7);
return inst_base;
}
ARM_INST_PTR INTERPRETER_TRANSLATE(uqadd16)(unsigned int inst, int index)
{
return INTERPRETER_TRANSLATE(uqadd8)(inst, index);
}
ARM_INST_PTR INTERPRETER_TRANSLATE(uqaddsubx)(unsigned int inst, int index)
{
return INTERPRETER_TRANSLATE(uqadd8)(inst, index);
}
ARM_INST_PTR INTERPRETER_TRANSLATE(uqsub8)(unsigned int inst, int index)
{
return INTERPRETER_TRANSLATE(uqadd8)(inst, index);
}
ARM_INST_PTR INTERPRETER_TRANSLATE(uqsub16)(unsigned int inst, int index)
{
return INTERPRETER_TRANSLATE(uqadd8)(inst, index);
}
ARM_INST_PTR INTERPRETER_TRANSLATE(uqsubaddx)(unsigned int inst, int index)
{
return INTERPRETER_TRANSLATE(uqadd8)(inst, index);
}
ARM_INST_PTR INTERPRETER_TRANSLATE(usad8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("USAD8"); }
ARM_INST_PTR INTERPRETER_TRANSLATE(usada8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("USADA8"); }
ARM_INST_PTR INTERPRETER_TRANSLATE(usat)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("USAT"); }
@ -6876,12 +6908,69 @@ unsigned InterpreterMainLoop(ARMul_State* state)
goto DISPATCH;
}
UQADD16_INST:
UQADD8_INST:
UQADD16_INST:
UQADDSUBX_INST:
UQSUB16_INST:
UQSUB8_INST:
UQSUB16_INST:
UQSUBADDX_INST:
{
INC_ICOUNTER;
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
const u8 op2 = inst_cream->op2;
const u32 rm_val = RM;
const u32 rn_val = RN;
u16 lo_val = 0;
u16 hi_val = 0;
// UQADD16
if (op2 == 0x00) {
lo_val = ARMul_UnsignedSaturatedAdd16(rn_val & 0xFFFF, rm_val & 0xFFFF);
hi_val = ARMul_UnsignedSaturatedAdd16((rn_val >> 16) & 0xFFFF, (rm_val >> 16) & 0xFFFF);
}
// UQASX
else if (op2 == 0x01) {
lo_val = ARMul_UnsignedSaturatedSub16(rn_val & 0xFFFF, (rm_val >> 16) & 0xFFFF);
hi_val = ARMul_UnsignedSaturatedAdd16((rn_val >> 16) & 0xFFFF, rm_val & 0xFFFF);
}
// UQSAX
else if (op2 == 0x02) {
lo_val = ARMul_UnsignedSaturatedAdd16(rn_val & 0xFFFF, (rm_val >> 16) & 0xFFFF);
hi_val = ARMul_UnsignedSaturatedSub16((rn_val >> 16) & 0xFFFF, rm_val & 0xFFFF);
}
// UQSUB16
else if (op2 == 0x03) {
lo_val = ARMul_UnsignedSaturatedSub16(rn_val & 0xFFFF, rm_val & 0xFFFF);
hi_val = ARMul_UnsignedSaturatedSub16((rn_val >> 16) & 0xFFFF, (rm_val >> 16) & 0xFFFF);
}
// UQADD8
else if (op2 == 0x04) {
lo_val = ARMul_UnsignedSaturatedAdd8(rn_val, rm_val) |
ARMul_UnsignedSaturatedAdd8(rn_val >> 8, rm_val >> 8) << 8;
hi_val = ARMul_UnsignedSaturatedAdd8(rn_val >> 16, rm_val >> 16) |
ARMul_UnsignedSaturatedAdd8(rn_val >> 24, rm_val >> 24) << 8;
}
// UQSUB8
else {
lo_val = ARMul_UnsignedSaturatedSub8(rn_val, rm_val) |
ARMul_UnsignedSaturatedSub8(rn_val >> 8, rm_val >> 8) << 8;
hi_val = ARMul_UnsignedSaturatedSub8(rn_val >> 16, rm_val >> 16) |
ARMul_UnsignedSaturatedSub8(rn_val >> 24, rm_val >> 24) << 8;
}
RD = ((lo_val & 0xFFFF) | hi_val << 16);
}
cpu->Reg[15] += GET_INST_SIZE(cpu);
INC_PC(sizeof(generic_arm_inst));
FETCH_INST;
GOTO_NEXT_INST;
}
USAD8_INST:
USADA8_INST:
USAT_INST:

65
src/core/arm/interpreter/armemu.cpp
View File

@ -6117,26 +6117,55 @@ L_stm_s_takeabort:
}
printf("Unhandled v6 insn: uasx/usax\n");
break;
case 0x66:
if ((instr & 0x0FF00FF0) == 0x06600FF0) { //uqsub8
u32 rd = (instr >> 12) & 0xF;
u32 rm = (instr >> 16) & 0xF;
u32 rn = (instr >> 0) & 0xF;
u32 subfrom = state->Reg[rm];
u32 tosub = state->Reg[rn];
case 0x66: // UQADD16, UQASX, UQSAX, UQSUB16, UQADD8, and UQSUB8
{
const u8 rd_idx = BITS(12, 15);
const u8 rm_idx = BITS(0, 3);
const u8 rn_idx = BITS(16, 19);
const u8 op2 = BITS(5, 7);
const u32 rm_val = state->Reg[rm_idx];
const u32 rn_val = state->Reg[rn_idx];
u8 b1 = (u8)((u8)(subfrom)-(u8)(tosub));
if (b1 > (u8)(subfrom)) b1 = 0;
u8 b2 = (u8)((u8)(subfrom >> 8) - (u8)(tosub >> 8));
if (b2 > (u8)(subfrom >> 8)) b2 = 0;
u8 b3 = (u8)((u8)(subfrom >> 16) - (u8)(tosub >> 16));
if (b3 > (u8)(subfrom >> 16)) b3 = 0;
u8 b4 = (u8)((u8)(subfrom >> 24) - (u8)(tosub >> 24));
if (b4 > (u8)(subfrom >> 24)) b4 = 0;
state->Reg[rd] = (u32)(b1 | b2 << 8 | b3 << 16 | b4 << 24);
u16 lo_val = 0;
u16 hi_val = 0;
// UQADD16
if (op2 == 0x00) {
lo_val = ARMul_UnsignedSaturatedAdd16(rn_val & 0xFFFF, rm_val & 0xFFFF);
hi_val = ARMul_UnsignedSaturatedAdd16((rn_val >> 16) & 0xFFFF, (rm_val >> 16) & 0xFFFF);
}
// UQASX
else if (op2 == 0x01) {
lo_val = ARMul_UnsignedSaturatedSub16(rn_val & 0xFFFF, (rm_val >> 16) & 0xFFFF);
hi_val = ARMul_UnsignedSaturatedAdd16((rn_val >> 16) & 0xFFFF, rm_val & 0xFFFF);
}
// UQSAX
else if (op2 == 0x02) {
lo_val = ARMul_UnsignedSaturatedAdd16(rn_val & 0xFFFF, (rm_val >> 16) & 0xFFFF);
hi_val = ARMul_UnsignedSaturatedSub16((rn_val >> 16) & 0xFFFF, rm_val & 0xFFFF);
}
// UQSUB16
else if (op2 == 0x03) {
lo_val = ARMul_UnsignedSaturatedSub16(rn_val & 0xFFFF, rm_val & 0xFFFF);
hi_val = ARMul_UnsignedSaturatedSub16((rn_val >> 16) & 0xFFFF, (rm_val >> 16) & 0xFFFF);
}
// UQADD8
else if (op2 == 0x04) {
lo_val = ARMul_UnsignedSaturatedAdd8(rn_val, rm_val) |
ARMul_UnsignedSaturatedAdd8(rn_val >> 8, rm_val >> 8) << 8;
hi_val = ARMul_UnsignedSaturatedAdd8(rn_val >> 16, rm_val >> 16) |
ARMul_UnsignedSaturatedAdd8(rn_val >> 24, rm_val >> 24) << 8;
}
// UQSUB8
else {
lo_val = ARMul_UnsignedSaturatedSub8(rn_val, rm_val) |
ARMul_UnsignedSaturatedSub8(rn_val >> 8, rm_val >> 8) << 8;
hi_val = ARMul_UnsignedSaturatedSub8(rn_val >> 16, rm_val >> 16) |
ARMul_UnsignedSaturatedSub8(rn_val >> 24, rm_val >> 24) << 8;
}
state->Reg[rd_idx] = ((lo_val & 0xFFFF) | hi_val << 16);
return 1;
} else {
printf ("Unhandled v6 insn: uqsub16\n");
}
break;
case 0x67: // UHADD16, UHASX, UHSAX, UHSUB16, UHADD8, and UHSUB8.

41
src/core/arm/interpreter/armsupp.cpp
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@ -469,6 +469,47 @@ ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result)
ASSIGNV (SubOverflow (a, b, result));
}
/* 8-bit unsigned saturated addition */
u8 ARMul_UnsignedSaturatedAdd8(u8 left, u8 right)
{
u8 result = left + right;
if (result < left)
result = 0xFF;
return result;
}
/* 16-bit unsigned saturated addition */
u16 ARMul_UnsignedSaturatedAdd16(u16 left, u16 right)
{
u16 result = left + right;
if (result < left)
result = 0xFFFF;
return result;
}
/* 8-bit unsigned saturated subtraction */
u8 ARMul_UnsignedSaturatedSub8(u8 left, u8 right)
{
if (left <= right)
return 0;
return left - right;
}
/* 16-bit unsigned saturated subtraction */
u16 ARMul_UnsignedSaturatedSub16(u16 left, u16 right)
{
if (left <= right)
return 0;
return left - right;
}
/* This function does the work of generating the addresses used in an
LDC instruction. The code here is always post-indexed, it's up to the
caller to get the input address correct and to handle base register

5
src/core/arm/skyeye_common/armdefs.h
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@ -790,6 +790,11 @@ extern void ARMul_FixSPSR(ARMul_State*, ARMword, ARMword);
extern void ARMul_ConsolePrint(ARMul_State*, const char*, ...);
extern void ARMul_SelectProcessor(ARMul_State*, unsigned);
extern u8 ARMul_UnsignedSaturatedAdd8(u8, u8);
extern u16 ARMul_UnsignedSaturatedAdd16(u16, u16);
extern u8 ARMul_UnsignedSaturatedSub8(u8, u8);
extern u16 ARMul_UnsignedSaturatedSub16(u16, u16);
#define DIFF_LOG 0
#define SAVE_LOG 0